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3 volt fast boot block flash memory 28f800f3?automotive preliminary datasheet product features the intel ? 3 volt fast boot block flash memory offers the highest performance synchronous burst reads ? making it an ideal memory solution for burst cpus. the intel 3 volt fast boot block flash memory also supports asynchronous page mode operation for non-clocked memory subsystems. combining high read performance with the intrinsic nonvolatility of flash memory eliminates the traditional redundant memory paradigm of shadowing code from a slower nonvolatile storage source to a faster execution memory device, (e.g., sram sdram), for improved system performance. by adding 3 volt fast boot block flash memory to your system you could reduce the total memory requirement, which helps increase reliability and reduce overall system power consumption ? all while reducing system cost. this family of products is manufactured on intel ? 0.4 m etox ? v process technology. they are available in a wide variety of industry-standard packaging technologies. high performance ? up to 50 mhz effective zero wait-state performance ? synchronous burst-mode reads ? asynchronous page-mode reads smartvoltage technology ? 3.0 v ? 3.6 v read and write operations for low power designs ? 12 v v pp fast factory programming enhanced data protection ? absolute write protection with v pp = gnd ? block locking ? block erase/program lockout during power transitions manufactured on etox ? v flash technology supports code plus data storage ? optimized for flash data integrator (fdi) and other intel ? software ? fast program suspend capability ? fast erase suspend capability flexible blocking architecture ? eight 4-kword blocks for data ? 32-kword main blocks for code ? top or bottom boot configurations extended cycling capability low power consumption automated program and block erase algorithms ? command user interface for automation ? status register for system feedback industry-standard packaging ? 56-lead ssop ? intel ? easy bga order number: 290686-003 march 2001 notice: this document contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
preliminary information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 28f800f3 may contain design defects or errors known as errata which may cause the product to deviate from published specifi cations. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation 2001. *other names and brands may be claimed as the property of others.
preliminary iii 228f800f3 ? automotive contents 1.0 introduction .................................................................................................................. 1 1.1 product overview .................................................................................................. 1 2.0 product description .................................................................................................. 2 2.1 pinouts .................................................................................................................. 2 2.2 pin description ...................................................................................................... 2 2.3 memory blocking organization ............................................................................. 5 2.3.1 parameter blocks ..................................................................................... 5 2.3.2 main blocks .............................................................................................. 5 3.0 principles of operation ............................................................................................ 7 3.1 bus operations...................................................................................................... 7 3.1.1 read......................................................................................................... 7 3.1.2 output disable.......................................................................................... 7 3.1.3 standby .................................................................................................... 8 3.1.4 write ......................................................................................................... 8 3.1.5 reset ........................................................................................................8 4.0 command definitions ............................................................................................... 9 4.1 read array command.........................................................................................10 4.2 read identifier codes command ........................................................................10 4.3 read status register command.........................................................................10 4.4 clear status register command.........................................................................11 4.5 block erase command........................................................................................11 4.6 program command .............................................................................................12 4.7 block erase suspend/resume command ..........................................................13 4.8 program suspend/resume command ...............................................................13 4.9 set read configuration command .....................................................................14 4.9.1 read configuration ? (rcr.15) .............................................................15 4.9.2 frequency configuration code setting (fcc) ? (rcr.13-11) ...............15 4.9.3 data output configuration ? (rcr.9) ....................................................17 4.9.4 wait # configuration ? (rcr.8)..............................................................18 4.9.5 burst sequence ? (rcr.7).....................................................................18 4.9.6 clock configuration ? (rcr.6) ...............................................................18 4.9.7 burst length ? (rcr.2 ? 0) ....................................................................19 4.9.8 continuous burst length........................................................................19 5.0 data protection .........................................................................................................24 5.1 vpp vpplk for complete protection...............................................................24 5.2 wp# = vil for block locking...............................................................................24 5.3 wp# = vih for block unlocking...........................................................................24 6.0 vpp voltages .............................................................................................................25 7.0 power consumption ...............................................................................................25 7.1 active power .......................................................................................................25 7.2 automatic power savings ...................................................................................25
28f800f3 ? automotive iv preliminary 7.3 standby power.................................................................................................... 25 7.4 power-up/down operation ................................................................................. 26 7.4.1 rst# connection................................................................................... 26 7.4.2 vcc, vpp and rst# transitions........................................................... 26 7.5 power supply decoupling ................................................................................... 26 7.5.1 vpp trace on printed circuit boards ..................................................... 27 8.0 electrical specifications ........................................................................................ 28 8.1 absolute maximum ratings ................................................................................ 28 8.2 automotive temperature operating conditions.................................................. 29 8.3 capacitance (1) ..................................................................................................... 29 8.4 dc characteristics ? automotive temperature (1) ................................................ 30 8.5 ac characteristics ? read-only operations (1,2) ? automotive temperature ...... 32 8.6 ac characteristics ? write operations (1, 2) ? automotive temperature .............. 38 8.7 ac characteristics ? reset operation ? automotive temperature ..................... 40 8.8 automotive temperature block erase and program performance (1,2,3) ............. 41 9.0 ordering information .............................................................................................. 42
preliminary v 228f800f3 ? automotive revision history date of revision version description 10/01/99 -001 original version 08/03/00 -002 removed all references to 5 v and 1.65 v i/o capability. removed -125 ns device and added 80ns device. changed t chqv time from 19 ns to 17 ns. changed t apa time from 35 ns to 25 ns. changed t ehqz/ghqv time from 25 ns to 23 ns. changed t dvwh time from 70 ns to 63 ns. changed block program and erase times in table 8.8. minor text edits. 03/26/01 -003 changed t chqv time for ? 95 device from 10ns to 19ns in table 8.5, ac charac- teristics?read-only operations (1,2) ?automotive temperature revised table 8.8, automotive temperature block erase and program performance (1,2,3)

28f800f3 ? automotive preliminary 1 1.0 introduction this datasheet contains 8-mbit 3 volt intel ? fast boot block flash memory information. section 1.0 provides a flash memory overview. sections 2.0 through 8.0 describe the memory functionality and electrical specifications for automotive temperature product offerings. 1.1 product overview the 3 volt fast boot block flash memory provides density upgrades with pinout compatibility for 8-mbit densities. this family of products is a high-performance, low-voltage memory with a 16-bit data bus and individually erasable blocks. these blocks are optimally sized for code and data storage. eight 4-kword parameter blocks are positioned at either the top (denoted by -t suffix) or bottom (denoted by -b suffix) of the address map. the rest of the device is grouped into 32-kword main blocks. the upper two (or lower two) parameter blocks, and all main blocks, can be locked when wp# = v il for complete code protection. the device ? s optimized architecture and interface dramatically increase read performance. it supports synchronous burst reads and asynchronous page mode reads from main blocks (parameter blocks support single synchronous and asynchronous reads). upon initial power-up or return from reset, the main blocks of the device default to a page-mode. page-mode is for non-clocked memory systems and is compatible with page-mode rom. synchronous burst reads are enabled by configuring the read configuration register using the standard two-bus-cycle algorithm. in synchronous burst mode, the clk input increments an internal burst address generator, synchronizes the flash memory with the host cpu, and outputs data on every rising (or falling) clk edge up to 50 mhz. an output signal, wait#, is also provided to ease cpu-to-flash memory communication and synchronization during continuous burst operations that are not initiated on a four-word boundary. in addition to the enhanced architecture and optimized interface, this family of products incorporates smartvoltage technology which enables fast 12 volt factory programming and 3.0 v ? 3.6 v in system programming for low power designs. specifically designed for low-voltage systems, 3 volt fast boot block flash memory components support read, write and erase operations at 3.0 v ? 3.6 v. the 12 v v pp option renders the fastest program performance to increase factory programming throughput. with the 3.0 v ? 3.6 v v pp option, v cc and v pp can be tied together for a simple, low power design. in addition to the voltage flexibility, the dedicated v pp pin gives complete data protection when v pp v pplk . the flexible input/output (i/o) voltage feature of the device helps reduce system power consumption and simplifies interfacing to sub 3.0 v cpus. powered by the v ccq pins, the i/o buffers can operate independently of the core voltage. the flexible i/o ring of the device works in the following mode: with v cc and v ccq at 3.0 v ? 3.6 v the device is an ideal fit for single supply voltage, low power, and battery-powered applications. the device ? s command user interface (cui) serves as the interface between the system processor and internal flash memory operation. a valid command sequence written to the cui initiates device automation. this automation is controlled by an internal write state machine (wsm) which automatically executes the algorithms and timings necessary for block erase and program operations. the status register provides wsm feedback by signifying block erase or program completion and status.
28f800f3 ? automotive 2 preliminary block erase and program automation allows erase and program operations to be executed using an industry-standard two-write command sequence. a block erase operation erases one block at a time, and data is programmed in word (16 bit) increments. the erase suspend feature allows system software to suspend an ongoing block erase operation in order to read from or program data to any other block. the program suspend feature allows system software to suspend an ongoing program operation in order to read from any other location. the 3 volt fast boot block flash memory devices offer two low-power savings features: automatic power savings (aps) and standby mode. the device automatically enters aps mode following the completion of a read cycle. standby mode is initiated when the system deselects the device by driving ce# inactive or rst# active. rst# also resets the device to read array, provides write protection, and clears the status register. combined, these two features significantly reduce power consumption. 2.0 product description this section describes the pinout and block architecture of the device family. 2.1 pinouts intel 3 volt fast boot block flash memory provides upgrade paths in each package pinout up to the 8-mbit density. the family is available in easy bga and 56-lead ssop packages. ballout for the easy bga is illustrated in figure 1 on page 3 . pinout for the 8-mbit, 56-lead ssop is illustrated in figure 2 on page 4 . 2.2 pin description the pin description table describes pin usage.
28f800f3 ? automotive preliminary 3 easypin01 notes: 1. a 20 is only valid on 32-mbit densities and above, a 21 is only valid on 64-mbit densities and above, a 22 is only valid on 128-mbit densities and above. all locations are populated with solder balls. 2. shaded connections on the top view indicate possible future upgrade address connections. 3. reference the preliminary mechanical specification for easy bga package at the intel ? flash packaging data website, http://developer.intel.com/design/flash/packdata/index.htm, for detailed package specifications. figure 1. 8 x 8 easy bga package ballout 1 2 3 4 5 6 7 8 a b c d e f g h top view - ball side down bottom view - ball side up a 1 a 6 a 18 v pp v cc gnd a 10 a 15 a 2 a 17 a 19 rst# clk a 20 (1) a 11 a 14 a 3 a 7 wp# we# adv# a 21 (1) a 12 a 13 a 4 a 5 du dq 8 dq 1 dq 9 dq 3 dq 12 dq 6 du du ce# dq 0 dq 10 dq 11 dq 5 dq 14 du du a 0 v ssq dq 2 dq 4 dq 13 dq 15 gnd a 16 a 22 (1) oe# v ccq v cc v ssq dq 7 v ccq wait# du du du a 8 a 9 8 7 6 5 4 3 2 1 a b c d e f g h a 15 a 10 gnd v cc v pp a 18 a 6 a 1 a 14 a 11 a 20 (1) clk rst# a 19 a 17 a 2 a 13 a 12 a 21 (1) adv# we# wp# a 7 a 3 a 9 a 8 du du du dq 6 dq 12 dq 3 dq 9 dq 1 dq 8 du du dq 14 dq 5 dq 11 dq 10 dq 0 ce# a 16 gnd d 15 d 13 dq 4 dq 2 v ssq a 0 wait# v ccq d 7 v ssq v cc v ccq oe# a 22 (1) du du du a 5 a 4
28f800f3 ? automotive 4 preliminary note: a 20 and a 21 are the upgrade addresses for potential 32-mbit and 64-mbit devices. figure 2. ssop pinout we# rst# v pp wp# nc a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 dq 9 dq 1 dq 8 dq 0 oe# gnd ce# a 0 nc v ccq dq 2 dq 10 dq 3 dq 11 v cc clk adv# gnd nc a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 nc gnd dq 6 dq 14 dq 7 dq 15 gnd v ccq a 16 wait# dq 13 dq 5 dq 12 dq 4 v cc 56-lead ssop 16 mm x 23.7 mm top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 8-mbit 8-mbit --a 20 32-mbit --a 21 64-mbit table 1. pin descriptions (sheet 1 of 2) sym type name and function a 0 ? a 19 input address inputs: inputs for addresses during read and write operations. addresses are internally latched during read and write cycles. 8-mbit: a 0 ? 18 dq 0 ? dq 15 input/ output data input/outputs: inputs data and commands during write cycles, outputs data during memory array, status register (dq 0 ? dq 7 ), and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. clk input clock: synchronizes the flash memory to the system operating frequency during synchronous burst mode read operations. when configured for synchronous burst-mode reads, the address is latched on the first rising (or falling, depending upon the read configuration register setting) clk edge when adv# is active or upon a rising adv# edge, whichever occurs first. clk is ignored during asynchronous page-mode read and write operations. adv# input address valid: indicates that a valid address is present on the address inputs. addresses are latched on the rising edge of adv# during read and write operations. adv# may be tied active during asynchronous read and write operations. ce# input chip enable: activates the device ? s control logic, input buffers, decoders, and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. rst# input reset: when driven low, rst# inhibits write operations which provides data protection during power transitions, and it resets internal automation. rst#-high enables normal operation. exit from reset sets the device to asynchronous read array mode. oe# input output enable: gates data outputs during a read cycle.
28f800f3 ? automotive preliminary 5 2.3 memory blocking organization the 3 volt fast boot block flash memory family is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. for the address locations of each block, see the memory maps in figure 3, ? 8- mbit top boot and bottom boot memory map ? on page 6 . 8-mbit top boot and bottom boot blocking. 2.3.1 parameter blocks the 3 volt fast boot block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters that would normally be stored in an eeprom. by using software techniques, the word-rewrite functionality of eeproms can be emulated. each 8- mbit device contains eight 4-kwords (4,096-words) parameter blocks. 2.3.2 main blocks after the parameter blocks, the remainder of the array is divided into equal size main blocks for code and/or data storage. the main blocks are the area of the device that support four-, eight-, and continuous burst operations. the 8-mbit device contains fifteen 32-kword (32,768-word) main blocks. we# input write enable: controls writes to the cui and array. addresses and data are latched on the rising edge of the we# pulse. wp# input write protection: provides a method for locking and unlocking all main blocks and two parameter blocks. when wp# is at logic low, lockable blocks are locked. if a program or erase operation is attempted on a locked block, sr.1 and either sr.4 [program] or sr.5 [block erase] will be set to indicate the operation failed. when wp# is at logic high, the lockable blocks are unlocked and can be programmed or erased. wait# output wait: provides data valid feedback only when configured for synchronous burst mode and the burst length is set to continuous. this signal is gated by oe# and ce# and is internally pull-up to v ccq via a resistor. wait# from several components can be tied together to form one system wait# signal. v pp supply block erase and program power supply (3.0 v?3.6 v, 11.4 v?12.6 v): for erasing array blocks or programming data, a valid voltage must be applied to this pin. with v pp v pplk , memory contents cannot be altered. block erase and program with an invalid v pp voltage should not be attempted. applying 11.4 v ? 12.6 v to v pp can only be done for a maximum of 1000 cycles on main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum (see section 6.0 for details). v cc supply device power supply (3.0 v ? 3.6 v): with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltages should not be attempted. v ccq supply output power supply (3.0 v ? 3.6 v): enables all outputs to be driven to 3.0 v to 3.6 v. gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated. (pins noted as possible upgrades to 32-mbit and 64-mbit densities can be connected to the appropriate address lines to pre- enable designs for possible future devices.). table 1. pin descriptions (sheet 2 of 2) sym type name and function
28f800f3 ? automotive 6 preliminary figure 3. 8- mbit top boot and bottom boot memory map 8-mbit 70000h - 77fffh 68000h - 6ffffh 60000h - 67fffh 58000h - 5ffffh 50000h - 57fffh 48000h - 4ffffh 40000h - 47fffh 38000h - 3ffffh 30000h - 37fffh 28000h - 2ffffh 20000h - 27fffh 18000h - 1ffffh 10000h - 17fffh 08000h - 0ffffh 00000h - 07fffh 4-kword parameter block 19 4-kword parameter block 20 4-kword parameter block 21 4-kword parameter block 22 parameter blocks 4-kword parameter block 18 4-kword parameter block 17 4-kword parameter block 16 4-kword parameter block 15 7f000h - 7ffffh 7e000h -7efffh 7d000h - 7dfffh 7c000h - 7cfffh 7b000h - 7bfffh 7a000h - 7afffh 79000h - 79fffh 78000h - 78fffh eeprom replacement lockable blocks 32-kword main block 0 32-kword main block1 32-kword main block 2 32-kword main block 3 32-kword main block 4 32-kword main block 5 32-kword main block 6 32-kword main block 7 32-kword main block 8 32-kword main block 9 32-kword main block 10 32-kword main block 11 32-kword main block 12 32-kword main block 13 32-kword main block 14 main blocks burstable area address range 32-kword main block 8 32-kword main block 9 32-kword main block 10 32-kword main block 11 32-kword main block 12 32-kword main block 13 32-kword main block 14 32-kword main block 15 32-kword main block 16 32-kword main block 17 32-kword main block 18 32-kword main block 19 32-kword main block 20 32-kword main block 21 32-kword main block 22 address range 8-mbit main blocks burstable area 78000h - 7ffffh 70000h - 77fffh 68000h - 6ffffh 60000h - 67fffh 58000h - 5ffffh 50000h - 57fffh 48000h - 4ffffh 40000h - 47fffh 38000h - 3ffffh 30000h - 37fffh 28000h - 2ffffh 20000h - 27fffh 18000h - 1ffffh 10000h - 17fffh 08000h - 0ffffh 4-kword parameter block 4 4-kword parameter block 5 4-kword parameter block 6 4-kword parameter block 7 parameter blocks 4-kword parameter block 3 4-kword parameter block 2 4-kword parameter block 1 4-kword parameter block 0 07000h - 07fffh 06000h - 06fffh 05000h - 05fffh 04000h - 04fffh 03000h - 03fffh 02000h - 02fffh 01000h - 01fffh 00000h - 00fffh eeprom replacement lockable blocks lockable blocks lockable blocks
28f800f3 ? automotive preliminary 7 3.0 principles of operation the 3 volt fast boot block flash memory components include an on-chip write state machine (wsm) to manage block erase and program. it allows for cmos-level control inputs, fixed power supplies, and minimal processor overhead with ram-like interface timings. 3.1 bus operations the local cpu reads and writes flash memory in-system. all flash memory read and write cycles conform to standard microprocessor bus cycles. 3.1.1 read the flash memory has three read modes available: read array, identifier codes, and status register. these modes are accessible independent of the v pp voltage. the appropriate read command (read array, read identifier codes, or read status register) must be written to the cui to enter the requested read mode. upon initial power-up or exit from reset, the device defaults to read array mode. when reading information from main blocks in read array mode, the device supports two high- performance read configurations: synchronous burst mode and asynchronous page mode. page mode and synchronous burst-mode reads are enabled by writing the set read configuration register command to any device address. synchronous burst mode is enabled by writing to the read configuration register. this sets the read configuration, burst order, burst length, and frequency configuration. in synchronous burst mode, the device latches the initial address then outputs a sequence of data with respect to the input clk and read configuration setting. synchronous burst reads can be terminated after one cycle in main blocks. asynchronous page mode is the default state and provides a high data transfer rate for non- clocked memory subsystems. in this state, data is internally read and stored in a high-speed page buffer. a 1:0 addresses data in the page buffer. the page size is four words. read operations from the parameter blocks, identifier codes and status register transpire as single- synchronous or asynchronous read cycles. the read configuration register setting determines whether or not read operations are synchronous or asynchronous. for all read operations, ce# must be driven active to enable the devices, adv# must be driven low to open the internal address latch, and oe# must be driven low to activate the outputs. in asynchronous mode, the address is latched when adv# is driven high. in synchronous mode, the address is latched by adv# going high or adv# low in conjunction with a rising (falling) clock edge, whichever occurs first. we# must be at v ih . figure 14 through figure 19 illustrate the different read cycles. 3.1.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0 ? dq 15 are placed in a high-impedance state.
28f800f3 ? automotive 8 preliminary 3.1.3 standby deselecting the device by bringing ce# to a logic-high level (v ih ) places the device in standby mode, which substantially reduces device power consumption. in standby, outputs are placed in a high-impedance state independent of oe#. if deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. 3.1.4 write commands are written to the cui using standard microprocessor write timings when adv#, we#, and ce# are active and oe# is inactive. the cui does not occupy an addressable memory location. the address is latched on the rising edge of adv#, we#, or ce# (whichever occurs first) and data needed to execute a command is latched on the rising edge of we# or ce# (whichever goes high first). write operations are asynchronous. therefore, clk is ignored during write operations. figure 20, ? ac waveform for write operations ? on page 39 illustrates a write operation. 3.1.5 reset the device enters a reset mode when rst# is driven low. in reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. after return from reset, a time t phqv is required until outputs are valid, and a delay (t phwl or t phel ) is required before a write sequence can be initiated. after this wake-up interval, normal operation is restored. the device defaults to read array mode, the status register is set to 80h, and the read configuration register defaults to asynchronous page-mode reads. if rst# is taken low during a block erase or program operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. see figure 21, ? ac waveform for reset operation ? on page 40 for detailed information regarding reset timings.
28f800f3 ? automotive preliminary 9 4.0 command definitions device operations are selected by writing specific commands into the cui. table 3 defines these commands. notes: 1. refer to dc characteristics . when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control and address input pins and v pplk or v pp1/2 for v pp . see dc characteristics for v pplk and v pp1/2 voltages. 3. command writes involving block erase or program are reliably executed when v pp = v pp1/2 and v cc = v cc1/2 (see section 8.0 for operating conditions at different temperatures). 4. refer to table 3 for valid d in during a write operation. notes: 1. commands other than those shown above are reserved by intel for future device implementations and should not be used. 2. bus operations are defined in table 2 . 3. x = any valid address within the device. ia = identifier code address. ba = address within the block being erased. wa = address of memory location to be written. rcd = data to be written to the read configuration register. this data is presented to the device on a 15-0 ; set all other address inputs to ? 0. ? table 2. bus operations mode notes rst# ce# adv# oe# we# address v pp dq 0 ? 15 reset v il xxxxxxhigh z standby v ih v ih xxxxxhigh z output disable v ih v il xv ih v ih x x high z read 1,2 v ih v il v il v il v ih xxd out read identifier codes v ih v il v il v il v ih see table 4 x see table 4 write 3,4 v ih v il v il v ih v il xxd in table 3. command definitions (1) command bus cycles required notes first bus cycle second bus cycle oper (2) addr (3) data (4) oper (2) addr (3) data (4) read array/reset 1 write x ffh read identifier codes 2 5 write x 90h read ia id read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 6,7 write x 20h write ba d0h program 2 6,7,8 write x 40h or 10h write wa wd block erase and program suspend 1 6 write x b0h block erase and program resume 1 6 write x d0h set read configuration 2 write rcd 60h write rcd 03h
28f800f3 ? automotive 10 preliminary 4. srd = data read from status register. see table 5, ? status register definition ? on page 12 for a description of the status register bits. wd = data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id = data read from identifier codes. see table 4 for manufacturer and device codes. rcd = data to be written to read configuration register. see table 6, ? read configuration register definition ? on page 14 for a description of the read configuration register bits. 5. following the read identifier codes command, read operations access manufacturer, device codes, and read configuration register. 6. following a block erase, program, and suspend operation, read operations access the status register. 7. to issue a block erase, program, or suspend operation to a lockable block, hold wp# at v ih . 8. either 40h or 10h are recognized by the wsm as the program setup. 4.1 read array command upon initial device power-up or exit from reset, the device defaults to read array mode. the read configuration register defaults to asynchronous page mode. the read array command also causes the device to enter read array mode. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase or program, the device will not recognize the read array command until the wsm completes its operation or unless the wsm is suspended via an erase or program suspend command. the read array command functions independently of the v pp voltage. 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. after writing the command, read cycles retrieve the manufacturer and device codes (see table 4 for identifier code values). page mode and burst reads are not supported in this read mode. to terminate the operation, write another valid command, like the read array command. the read identifier codes command functions independently of the v pp voltage. note: 1. read configuration register = rcd. 4.3 read status register command the status register can be read at any time by writing the read status register command to the cui. after writing this command, all subsequent read operations output status register data until another valid command is written. page mode and burst reads are not supported in this read mode. the status register content is updated and latched on the rising edge of adv# or rising (falling) table 4. identifier codes code address (hex) data (hex) manufacturer code 00000 0089 device code 8 mbit -t 00001 88f1 -b 00001 88f2 read configuration register 00005 rcd (1)
28f800f3 ? automotive preliminary 11 clk edge when adv# is low during synchronous burst mode or the falling edge of oe# or ce#, whichever occurs first. the read status register command functions independently of the v pp voltage. 4.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to ? 1 ? s by the wsm and can only be cleared by issuing the clear status register command. these bits indicate various error conditions. by allowing system software to reset these bits, several operations may be performed (such as cumulatively erasing or writing several bytes in sequence). the status register may be polled to determine if a problem occurred during the sequence. the clear status register command functions independently of the applied v pp voltage. after executing this command, the device returns to read array mode. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is written first, followed by a block erase confirm. this command sequence requires appropriate sequencing and address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm. after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 7, ? automated block erase flowchart ? on page 20 ). the cpu can detect block erase completion by analyzing status register bit sr.7. when the block erase completes, check status register bit sr.5 for an error flag ( ? 1 ? ). if an error is detected, check status register bits sr.4, sr.3, and sr.1 to understand what caused the failure. after examining the status register, it should be cleared if an error was detected before issuing a new command. the device will remain in status register read mode until another command is written to the cui.
28f800f3 ? automotive 12 preliminary 4.6 program command program operation is executed by a two-cycle command sequence. program setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data. the wsm then takes over, controlling the internal program algorithm. after the program sequence is written, the device automatically outputs status register data when read (see figure 8, ? automated program flowchart ? on page 21 ). the cpu can detect the completion of the program event by analyzing status register bit sr.7. when the program operation completes, check status register bit sr.4 for an error flag ( ? 1 ? ). if an error is detected, check status register bits sr.5, sr.3, and sr.1 to understand what caused the problem. after examining the status register, it should be cleared if an error was detected before issuing a new command. the device will remain in status register read mode until another command is written to the cui. table 5. status register definition wsms ess es ps vpps pss dps r 76543210 notes: sr.7 = write state machine status (wsms) 1 = ready 0 = busy check sr.7 to determine block erase or program completion. sr.6 ? 0 are invalid while sr.7 = ? 0. ? sr.6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed when an erase suspend command is issued, the wsm halts execution and sets both sr.7 and sr.6 to ? 1. ? sr.6 remains set until an erase resume command is written to the cui. sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase if both sr.5 and sr.4 are ? 1 ? s after a block erase or program attempt, an improper command sequence was entered. sr.4 = program status (ps) 1 = error in program 0 = successful program sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.3 does not provide a continuous v pp feedback. the wsm interrogates and indicates the v pp level only after a block erase or program operation. sr.3 is not guaranteed to report accurate feedback when v pp v pph1/2 or v pplk . sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when a program suspend command is issued, the wsm halts execution and sets both sr.7 and sr.2 to ? 1. ? sr.2 remains set until a program resume command is written to the cui. sr.1 = device protect status (dps) 1 = block erase or program attempted on a locked block, operation abort 0 = unlocked if a block erase or program operation is attempted on a locked block, sr.1 is set by the wsm and aborts the operation if wp# = v il . sr.0 = reserved for future enhancements (r) sr.0 is reserved for future use and should be masked out when polling the status register.
28f800f3 ? automotive preliminary 13 4.7 block erase suspend/resume command the block erase suspend command allows block erase interruption to read or program data in another block. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase operation after a certain latency period. the device continues to output status register data when read after the block erase suspend command is issued. status register bits sr.7 and sr.6 indicate when the block erase operation has been suspended (both will be set to ? 1 ? ). specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. a program command sequence can also be issued during erase suspend to program data in other blocks. using the program suspend command (see section 4.8 ), a program operation can be suspended during an erase suspend. the only other valid commands while block erase is suspended are read status register and block erase resume. during a block erase suspend, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. v pp must remain at v pp1/2 while block erase is suspended. wp# must also remain at v il or v ih . to resume the block erase operation, write the block erase resume command to the cui. this will automatically clear status register bits sr.6 and sr.7. after the erase resume command is written, the device automatically outputs status register data when read (see figure 9, ? block erase suspend/resume flowchart ? on page 22 ). block erase cannot resume until program operations initiated during block erase suspend have completed. 4.8 program suspend/resume command the program suspend command allows program interruption to read data in other flash memory locations. once the program process starts, writing the program suspend command requests that the wsm suspend the program operation after a certain latency period. the device continues to output status register data when read after issuing the program suspend command. status register bits sr.7 and sr.2 indicate when the program operation has been suspended (both will be set to ? 1 ? ). specification t whrh1 defines the program suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. the only other valid commands while program is suspended are read status register and program resume. during a program suspend, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. v pp must remain at v pp1/2 while program is suspended. wp# must also remain at v il or v ih . to resume the program, write the program resume command to the cui. this will automatically clear status register bits sr.7 and sr.2. after the program resume command is written, the device automatically outputs status register data when read (see figure 10, ? program suspend/resume flowchart ? on page 23 ).
28f800f3 ? automotive 14 preliminary 4.9 set read configuration command the set read configuration command writes data to the read configuration register. this operation is initiated by a standard two bus cycle command sequence. the read configuration setup command (60h) is written and the data to be written to the read configuration is presented, which is then followed by a second write that confirms the operation and again presents the data to be written to the read configuration register. the read configuration register data is placed on the address bus, a 15:0 ,during both bus cycles and is latched on the rising edge of adv#, ce#, or we# (whichever occurs first). the read configuration register data sets the device ? s read configuration, burst order, frequency configuration, burst length and all other parameters. this command functions independently of the applied v pp voltage. after executing this command, the device returns to read array mode. table 6. read configuration register definition rm r fc2 fc1 fc0 r doc wc 15 14 13 12 11 10 9 8 bs cc r r r bl2 bl1 bl0 76543210 notes: rcr.15 = read mode (rm) 0 = synchronous burst reads enabled 1 = page mode reads enabled (default) read mode configuration affects reads from main blocks. parameter block, status register, and identifier reads support single read cycles. rcr.14 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to ? 0. ? rcr.13 ? 11 = frequency configuration (fc2-0) 001 = code 1 reserved for future use 010 = code 2 011 = code 3 100 = code 4 101 = code 5 110 = code 6 see section 4.9.2 for information about the frequency configuration and its effect on the initial read. undocumented combinations of bits rcr.14 ? 11 are reserved by intel corporation for future implementations and should not be used. rcr.10 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to ? 0. ? rcr.9 = data output configuration (doc) 0 = hold data for one clock 1 = hold data for two clocks undocumented combinations of bits rcr.10 ? 9 are reserved by intel corporation for future implementations and should not be used. rcr.8 = wait configuration (wc) 0 = wait# asserted during delay 1 = wait# asserted one data cycle before delay rcr.7 = burst sequence (bs) 0 = intel burst order 1 = linear burst order rcr.6 = clock configuration (cc) 0 = burst starts and data output on falling clock edge 1 = burst starts and data output on rising clock edge rcr.5 ? 3 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to ? 0. ? rcr.2 ? 0 = burst length (bl2 ? 0) 001 = 4 word burst 010 = 8 word burst 111 = continuous burst in the asynchronous page mode, the burst length always equals four words. undocumented combinations of bits rcr.2 ? 0 are reserved by intel corporation for future implementations and should not be used
28f800f3 ? automotive preliminary 15 4.9.1 read configuration ? (rcr.15) the device supports two high performance read configurations: synchronous burst mode and asynchronous page mode. bit rcr.15 in the read configuration register sets the read configuration to either synchronous burst or asynchronous page mode. asynchronous page mode is the default read configuration state. parameter blocks, status register, and identifier modes only support single-synchronous and asynchronous read operations. 4.9.2 frequency configuration code setting (fcc) ? (rcr.13-11) the frequency configuration code setting informs the device of the number of clocks that must elapse after adv# is driven active before data will be available. this value is determined by the input clock frequency and the set up and hold requirements of the target system. see table 7, ? frequency configuration settings ? on page 17 for the specific input clk frequency configuration codes. the frequency configuration codes in table 7 are derived from equations (1), (2) and (3) with assumed values for the t avqv, t add, t data parameters. below is the example of the calculation to obtain the frequency configuration code: flash performance can be determined by the following equations: {1/frequency (mhz)} = clk period (ns) (1) n(clk period) t avqv (ns) + t add (ns) + t data (ns) (2) n-2 = frequency configuration code (fcc) * (3) n : # of clock periods (rounded up to the next integer) * must use fcc = n - 1 when operating in the continous burst mode. parameters defined by cpu : t add = clock to ce#, adv#, or address valid whichever occurs last. t data = data set up to clock parameters defined by flash : t avqv = address to output delay example : cpu clock speed = 40 mhz t add = 6 ns (typical speed from cpu) (max) t data = 4 ns (typical speed from cpu) (min) t avqv = 95 ns (from section 8.5 ac characteristic - read only operations table) from eq. (1): {1/40 (mhz)} = 25 ns from eq. (2) n(25 ns) 95 ns + 6 ns + 4 ns n(25 ns) 105 ns n 105/25 5 (integer) from eq. (3) n - 2 = 5 - 2 = 3 frequency code setting to the rcr is code 3 the formula t avqv (ns) + t add (ns) + t data (ns) is also known as initial access time.
28f800f3 ? automotive 16 preliminary note: 1. figure 4 shows the data output available and valid after 4 latencies from adv# going low in the 1st clock period with the fcc setting at 3. figure 5 illustrates data output latency from adv# going active for different frequency configuration codes. figure 4. data output with fcc setting at code 3 a 15-0 valid address dq 15-0 (d/q) clk (c) ce# adv# r13 valid output valid output high z t add t data 2nd 1st 3rd 4th 5th figure 5. frequency configuration adv# (v) a 19-0 (a) valid address clk (c) dq 15-0 (d/q) valid output dq 15-0 (d/q) valid output valid output valid output valid output dq 15-0 (d/q) valid output valid output valid output valid output dq 15-0 (d/q) valid output valid output dq 15-0 (d/q) valid output valid output valid output valid output code 2 code 3 code 4 code 5 code 6
28f800f3 ? automotive preliminary 17 note: table derived by using formulas (1), (2) and (3) in section 4.9.2 . values of t add , t data defined by cpu, assumed to be 6 ns and 4 ns respectively; value of t avqv per section 8.5 . 4.9.3 data output configuration ? (rcr.9) the output configuration determines the number of clocks during which data will be held valid. the data hold time is configurable as either one or two clocks. subsequent reads in burst mode with zero wait-states can be defined by: t chqv (ns) + t data (ns) one clk period in table 7 , consider the cpu clock at 40 mhz, and fcc is 3. the clock period is 25 ns. this data applied to the formula above for the subsequent reads assuming the data output hold time is one clock: 19 ns + 4 ns 25 ns data output will be available and valid at every clock period. consider the cpu frequency at 60 mhz, and fcc is 5. clock period is 16.6 ns. the initial access time is calculated to be 125 ns (5 latencies). this condition satisfies t av q v (ns) + t add (ns) + t data (ns) = 95 ns + 6 ns + 4 ns = 105 ns. however, the data output hold time of one clock violates burst data output zero wait-states: t chqv (ns) + t data (ns) one clk period 19 ns + 4 ns = 23 ns is not less than one clock period. to satisfy the formula above the data output hold time must be set a 2 clocks to correctly allow for data output setup time. in page mode reads the initial access time can be determined by the formula: t add (ns) + t data (ns) + t avqv (ns) and subsequent reads in page mode are defined by: t apa (ns) + t data (ns) (minimum time) table 7. frequency configuration settings frequency configuration code input clk frequency ? 80 ? 95 1 reserved reserved 2 38 mhz 29 mhz 3 47 mhz 37 mhz 4 57 mhz 44 mhz 5 66 mhz 51 mhz 6 ? 59 mhz
28f800f3 ? automotive 18 preliminary 4.9.4 wait # configuration ? (rcr.8) the wait# configuration bit controls the behavior of the wait# output signal. this output signal can be set to be asserted during or one clk cycle before an output delay when continuous burst length is enabled. its setting will depend on the system and cpu characteristic. 4.9.5 burst sequence ? (rcr.7) the burst sequence specifies the order in which data is addressed in synchronous burst mode. this order is programmable as either linear or intel burst order. the continuous burst length only supports linear burst order. the order chosen will depend on the cpu characteristic. see table 8 for more details. 4.9.6 clock configuration ? (rcr.6) the clock configuration configures the device to start a burst cycle, output data, and assert wait# on the rising or falling edge of the clock. clk flexibility helps ease 3 volt fast boot block flash memory interface to a wide range of burst cpus. figure 6. output configuration dq 15-0 (d/q) valid output dq 15-0 (d/q) valid output valid output valid output clk (c) 1 clk data hold 2 clk data hold table 8. sequence and burst length starting addr. (dec.) burst addressing sequence (dec.) 4-word burst length 8-word burst length continuous burst linear intel linear intel linear 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-... 3 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-.. 5 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-... 6 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-... 7 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-... 8 na 8-9-10-11-12-13-14-... 9 na ... 15 na 15-16-17-18-19-20-21-...
28f800f3 ? automotive preliminary 19 4.9.7 burst length ? (rcr.2 ? 0) the burst length is the number of words that the device will output. the device supports burst lengths of four and eight words. in four- or eight-word burst configuration the device will perform a wrap around type burst access (see table 8 ). it also supports a continuous burst mode. in continuous burst mode, the device will linearly output data until the internal burst counter reaches the end of the device ? s burstable address space. bits rcr.2 ? 0 in the read configuration register set the burst length. 4.9.8 continuous burst length when operating in the continuous burst mode, the flash memory may incur an output delay when the burst sequence crosses the first 16-word boundary. the starting address dictates whether or not a delay will occur. if the starting address is aligned to a four-word boundary, the delay will not be seen. if the starting address is the end of a four-word boundary, the output delay will be equal to the frequency configuration setting; this is the worst case delay. the delay will only take place once during a continuous burst access, and if the burst sequence never crosses a 16-word boundary, the delay will never happen. using the wait# output pin in the continuous burst configuration, the system is informed if this output delay occurs.
28f800f3 ? automotive 20 preliminary figure 7. automated block erase flowchart suspend blk. erase loop start write 20h, block address write d0h, block address read status register sr.7 = full status check if desired block erase complete full status check procedure repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last operation to place device in read array mode. sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear staus register command, in cases where multiple blocks are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend block erase 1 0 comments data = 20h addr = within block to be erased data = d0h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy comments check sr.3 1 = v pp error detect check sr.1 1 = device protect detect wp# = v il read status register data (see above) v pp range error device protect error block erase successful sr.3 = sr.1 = 1 0 1 0 command sequence error sr.4, 5 = 1 0 block erase error sr.5 = 1 0 status register data check sr.4, 5 both 1 = command sequence error check sr.5 1 = block erase error bus operation write write standby read command erase setup erase confirm bus operation standby standby standby standby command
28f800f3 ? automotive preliminary 21 figure 8. automated program flowchart suspend program loop start write 40h, address write data and address read status register sr.7 = full status check if desired program complete full status check procedure repeat for subsequent byte writes. sr full status check can be done after each byte write or after a sequence of program operations. write ffh after the last byte write operation to place device in read array mode. sr.4, sr.3 and sr.1 are only cleared by the clear staus register command, in cases where multiple locations are written before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend program 1 0 comments data = 40h addr = location to be written data = data to be written addr = location to be written check sr.7 1 = wsm ready 0 = wsm busy comments check sr.3 1 = v pp error detect check sr.1 1 = device protect detect wp# = v il read status register data (see above) v pp range error device protect error program successful sr.3 = sr.1 = 1 0 1 0 program error sr.4 = 1 0 status register data check sr.4 1 = data write error bus operation write write standby read command program setup data bus operation standby standby standby command
28f800f3 ? automotive 22 preliminary figure 9. block erase suspend/resume flowchart start write b0h read status register comments data = b0h addr = x data = d0h addr = x sr.7 = sr.6 = block erase completed write ffh read array data 0 1 0 status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = block erase suspended 0 = block erase completed read or byte write? command erase suspend erase resume bus operation write write read standby standby yes program program loop done write d0h block erase resumed read read array data no 1 data = ffh addr = x read array or program write read array or program loop
28f800f3 ? automotive preliminary 23 figure 10. program suspend/resume flowchart start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.2 = 1 write ffh read array data program completed done reading yes write ffh write d0h program resumed read array data 0 1 0 read array locations from block other than that being written status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = program suspended 0 = program completed data = d0h addr = x bus operation write write read read standby standby write command program suspend read array program resume
28f800f3 ? automotive 24 preliminary 5.0 data protection the 3 volt fast boot block flash memory architecture features two hardware-lockable parameter blocks, so critical code can be kept secure while six other parameter blocks can be programmed or erased as necessary to facilitate eeprom emulation. 5.1 v pp v pplk for complete protection the v pp programming voltage can be held low for complete write protection of all blocks in the flash device. when v pp is below v pplk , any block erase or program operation will result in a error, prompting the corresponding status register bit (sr.3) to be set. 5.2 wp# = v il for block locking the lockable blocks are locked when wp# = v il ; any block erase or program operation to a locked block will result in an error, which will be reflected in the status register. for top configuration, the top two parameter blocks (blocks #21, #22) and all main blocks are lockable. for the bottom configuration, the bottom two parameter blocks (blocks #0, #1) and all main blocks are lockable. unlocked blocks can be programmed or erased normally (unless v pp is below v pplk ). 5.3 wp# = v ih for block unlocking wp# controls all block locking and v pp provides protection against spurious writes. table 9 defines the write protection methods. table 9. write protection truth table v pp wp# rst# write protection provided xxv il all blocks locked v il xv ih all blocks locked v pplk v il v ih lockable blocks locked v pplk v ih v ih all blocks unlocked
28f800f3 ? automotive preliminary 25 6.0 v pp voltages intel 3 volt fast boot block flash memory provides in-system programming and erase at 3.0 v ? 3.6 v. for customers requiring fast programming in their manufacturing environment, this family of products includes an additional high-performance 12 v programming feature. the 12 v v pp mode enhances programming performance during short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 v may be applied to v pp during block erase and program operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. stressing the device beyond these limits may cause permanent damage. 7.0 power consumption while in operation, the flash device consumes active power. however, intel ? flash devices have power savings that can significantly reduce overall system power consumption. the automatic power savings (aps) feature reduces power consumption when the device is idle. when ce# is not asserted, the flash enters its standby mode, where current consumption is even lower. the combination of these features minimizes overall memory power and system power consumption. 7.1 active power with ce# at a logic-low level and rst# at a logic-high level, the device is in active mode. active power is the largest contributor to overall system power consumption. minimizing active current has a profound effect on system power consumption, especially for battery-operated devices. 7.2 automatic power savings automatic power savings (aps) provides low-power operation during active mode, allowing the flash to put itself into a low current state when not being accessed. after data is read from the memory array, the device ? s power consumption enters the aps mode where typical i cc current is comparable to i ccs . the flash stays in this static state with outputs valid until a new location is read. 7.3 standby power with ce# at a logic-high level (v ih ) and the cui in read mode, the flash memory is in standby mode, which disables much of the device ? s circuitry and substantially reduces power consumption. outputs (dq 0 ? dq 15 ) are placed in a high-impedance state independent of the status of the oe# signal. if ce# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed.
28f800f3 ? automotive 26 preliminary system engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. this will provide a more accurate measure of application-specific power and energy requirements. 7.4 power-up/down operation the device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required, since the device is indifferent as to which power supply, v pp , v cc , or v ccq , powers-up first. 7.4.1 rst# connection the use of rst# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. intel recommends connecting rst# to the system reset signal to allow proper cpu/flash initialization following system reset. system designers must guard against spurious writes when v cc voltages are above v lko and v pp is active. since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rst# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 7.4.2 v cc , v pp and rst# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from deep power-down mode or after v cc transitions above v lko (lockout voltage), is read array mode. after any block erase or program operation is complete (even after v pp transitions down to v pplk ), the cui must be reset to read array mode via the read array command if access to the flash memory array is desired. 7.5 power supply decoupling flash memory ? s power switching characteristics require careful device de-coupling. system designers should consider three supply current issues: standby current levels (i ccs ) active current levels (i ccr ) transient peaks produced by falling and rising edges of ce#.
28f800f3 ? automotive preliminary 27 transient current magnitudes depend on the device outputs ? capacitive and inductive loading. two- line control and proper de-coupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 7.5.1 v pp trace on printed circuit boards designing for in-system writes to the flash memory requires special consideration of the v pp power supply trace by the printed circuit board designer. the v pp pin supplies the flash memory cells current for programming and erasing. v pp trace widths and layout should be similar to that of v cc . adequate v pp supply traces, and de-coupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
28f800f3 ? automotive 28 preliminary 8.0 electrical specifications 8.1 absolute maximum ratings notes: 1. all specified voltages are with respect to gnd. minimum dc voltage is ? 0.5 v on input/output pins and ? 0.2 v on v cc and v pp pins. during transitions, this level may undershoot to ? 2.0 v for periods <20 ns. maximum dc voltage on input/output pins is 5.5 v and v cc and v ccq is v cc + 0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0 v for periods <20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. v pp program voltage is normally 3.0 v ? 3.6 v. connection to supply of 11.4 v ? 12.6 v can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. v pp may be connected to 12 v for a total of 80 hours maximum. warning: stressing the device beyond the ? absolute maximum ratings ? may cause permanent damage. these are stress ratings only. operation beyond the ? operating conditions ? is not recommended and extended exposure beyond the ? operating conditions ? may affect device reliability. parameter maximum rating temperature under bias ? 40 c to +125 c storage temperature ? 65 c to +125 c voltage on any pin (except v cc , v ccq , and v pp ) ? 0.5 v to +5.5 v (1) v pp voltage ? 0.5 v to +13.5 v (1, 2, 4) v cc and v ccq voltage ? 0.2 v to +5.0 v (1) output short circuit current 100 ma (3) notice: this datasheet contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design .
28f800f3 ? automotive preliminary 29 8.2 automotive temperature operating conditions notes: 1. see dc characteristics tables for voltage range-specific specifications. 2. the voltage swing on the inputs, v in is required to match v ccq . 3. applying v pp = 11.4 v ? 12.6 v during a program/erase can only be done for a maximum of 1000 cycles on the main and 2500 cycles on the parameter blocks. a hard connection to v pp = 11.4 v ? 12.6 v is not allowed and can cause damage to the device. 8.3 capacitance (1) t a = +25 c, f = 1 mhz note: 1. sampled, not 100% tested. symbol parameter notes min max unit t a operating temperature ? 40 +125 c v cc1 v cc supply voltage 1 3.0 3.6 v v ccq 1 i/o voltage 1,2 3.0 3.6 v v pp1 v pp supply voltage 1 3.0 3.6 v v pp2 v pp supply voltage 1,3 11.4 12.6 v cycling parameter block erase cycling 50,000 cycles main block erase cycling 1,000 cycles symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v
28f800f3 ? automotive 30 preliminary 8.4 dc characteristics ? automotive temperature (1) notes: 1. all currents are in rms unless otherwise noted. typical values at normal v cc , t a = +25 c. 2. erases and program operations are inhibited when v pp v pplk , and not guaranteed outside the valid v pp ranges of v pp1 and v pp2 . 3. sampled, not 100% tested. 4. automatic power savings (aps) reduces i ccr to approximately standby levels, in static operation. 5. 12 v (11.4 v ? 12.6 v) can only be applied to v pp for a maximum of 80 hours over the lifetime of the device. v pp should not be permanently tied to 12 v. 6. the specification is the sum of v cc and v ccq currents. sym parameter note typ max unit test condition i ccs v cc standby current 2,6 40 100 a v cc = v cc max v ccq = v ccq max ce# = rst# = v ih = v cc i ccr v cc read current 4,6 30 60 ma asynchronous t avqv = min v cc = v cc max v ccq = v ccq max v in = v ih or v il ce# = v il oe# = v ih 30 60 ma synchronous clk = 33 mhz ce# = v il oe# = v ih burst length = 8 i ccw v cc program current 3,5,7 820mav pp = v pp1 (3.0 v ? 3.6 v) program in progress 820mav pp = v pp2 (11.4 v ? 12.6 v) program in progress i cce v cc block erase current 3,5,7 820mav pp = v pp1 (3.0 v ? 3.6 v) block erase in progress 820mav pp = v pp2 (11.4 v ? 12.6 v) block erase in progress i ppw v pp program current 3,5,7 15 40 ma v pp = v pp1 (3.0 v ? 3.6 v) program in progress 10 25 ma v pp = v pp2 (11.4 v ? 12.6 v) program in progress i ppe v pp block erase current 3,5,7 13 25 ma v pp = v pp1 (3.0 v ? 3.6 v) block erase in progress 825mav pp = v pp2 (11.4 v ? 12.6 v) block erase in progress
28f800f3 ? automotive preliminary 31 note: ac test inputs are driven at 3.0 v for a logic "1" and 0.0 v for a logic "0." input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed conditions are when v ccq = 3.0 v. note: see table for component values. test configuration component value for worst case speed conditions note: c l includes jig capacitance. figure 11. ac input/output reference waveform for v cc = 3.3 v 0.3 v v ccq 0v v ccq /2 v ccq /2 t e s t p o i n t s input output figure 12. ac equivalent testing load circuit device under test v ccq c l r 2 r 1 out test configuration c l (pf) r 1 ( ? ) r 2 ( ? ) 3 v automotive test 80 25k 25k 3 v standard test 50 25k 25k
28f800f3 ? automotive 32 preliminary 8.5 ac characteristics ? read-only operations (1,2) ? automotive temperature notes: 1. see figure 11, ? ac input/output reference waveform for vcc = 3.3 v 0.3 v ? on page 31 for timing measurements and maximum allowable input slew rate. 2. data bus voltage must be less than or equal to v ccq when a read operation is initiated to guarantee ac specifications. 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is defined as t chax or t vhax , whichever timing specification is satisfied first. 5. oe# may be delayed up to t elqv ? t glqv after the falling edge of ce# without impact on t elqv . 6. adv# tied to ground, t ehel (ce# high pulse width) must be held high for a minimum of 15 ns. # symbol parameter product ? 80 ? 95 unit v cc 3.0 v ? 3.6 v 3.0 v ? 3.6 v notes min max min max r1 t clk clk period 15 15 ns r2 t ch (t cl ) clk high (low) time 2.5 2.5 ns r3 t chcl clk fall (rise) time 5 5 ns r4 t avch address valid setup to clk 10 10 ns r5 t vlch adv# low setup to clk 10 10 ns r6 t elch ce# low setup to clk 10 10 ns r7 t chqv clk to output delay 17 19 ns r8 t chqx output hold from clk 3 3 3 ns r9 t chax address hold from clk 4 10 10 ns r10 t chtl clk to wait# delay 3 19 19 ns r11 t avvh address setup to adv# high 10 10 ns r12 t elvh ce# low to adv# high 10 10 ns r13 t avqv address to output delay 80 95 ns r14 t elqv ce# low to output delay 5 80 95 ns r15 t vlqv adv# low to output delay 80 95 ns r16 t vlvh adv# pulse width low 10 10 ns r17 t vhvl adv# pulse width high 10 10 ns r18 t vhax address hold from adv# high 4 3 3 ns r19 t apa page address access time 25 25 ns r20 t glqv oe# low to output delay 40 40 ns r21 t phqv rst# high to output delay 600 600 ns r22 t ehqz t ghqz ce# or oe# high to output in high z, whichever occurs first 32325ns r23 t oh output hold from address, ce#, or oe# change, whichever occurs first 30 0 ns r24 t ehel ce# high pulse width 6 0 0 ns
28f800f3 ? automotive preliminary 33 figure 13. ac waveform for clk input figure 14. ac waveform for single asynchronous read operations from parameter blocks, status register, identifier codes r1 r2 r3 clk (c) r18 a 19-0 (a) v ih v il valid address r11 r13 r20 r23 dq 15-0 (d/q) rst# (r) r21 v ih v il v oh v ol valid output high z oe# (g) we# (w) v ih v il v ih v il wait# (t) v oh v ol r15 r16 adv# (v) v ih v il r17 r12 r14 r22 ce# (e) v ih v il
28f800f3 ? automotive 34 preliminary figure 15. ac waveform for asynchronous page mode read operations from main blocks r18 r11 r15 r13 r22 a 19-2 (a) a 1-0 (a) adv# (v) ce# (e) v ih v il v ih v il v ih v il v ih v il valid address valid address valid address valid address valid address r14 oe# (g) we# (w) v ih v il v ih v il wait# (t) v oh v ol r20 r19 r23 dq 15-0 (d/q) rst# (r) r21 v ih v il v oh v ol valid output valid output valid output valid output high z r17
28f800f3 ? automotive preliminary 35 notes: 1. 1.depending upon the frequency configuration code value in the read configuration register, insert clock cycles: ? frequency configuration 2 insert two clock cycles ? frequency configuration 3 insert three clock cycles ? frequency configuration 4 insert four clock cycles ? frequency configuration 5 insert five clock cycles ? frequency configuration 6 insert six clock cycles see section 4.9.2 for further information about the frequency configuration and its effect on the initial read. figure 16. ac waveform for single synchronous read operations from parameter blocks, status register, identifier codes v ih v il clk [c] a 19-0 [a] v ih v il r4 r12 r18 r11 r16 r22 adv# [v] ce# [e] v ih v il v ih v il r6 r5 oe# [g] we# [w] v ih v il v ih v il wait# [t] v oh v ol r20 r7 r23 dq 15-0 [d/q] v oh v ol r9 r13 r15 r14 r8 valid address high z valid output r17 note 1
28f800f3 ? automotive 36 preliminary notes: 1. 1.depending upon the frequency configuration code value in the read configuration register, insert clock cycles: ? frequency configuration 2 insert two clock cycles ? frequency configuration 3 insert three clock cycles ? frequency configuration 4 insert four clock cycles ? frequency configuration 5 insert five clock cycles ? frequency configuration 6 insert six clock cycles see section 4.9.2 for further information about the frequency configuration and its effect on the initial read. figure 17. ac waveform for synchronous burst read operations, four-word burst length, from main blocks v ih v il clk (c) note 1 a 19-0 (a) v ih v il valid address r4 r18 r11 r9 r12 r16 r22 adv# (v) ce# (e) v ih v il v ih v il r6 r5 oe# (g) we# (w) v ih v il v ih v il wait# (t) v oh v ol r20 r7 r8 r23 dq 15-0 (d/q) v oh v ol valid output valid output valid output valid output high z r17
28f800f3 ? automotive preliminary 37 notes: 1. this delay will only occur when burst length is configured as continuous. see section 4.9.7 for further information about burst length configuration. 2. wait# is configurable. it can be set to assert during or one clk cycle before an output delay. see section for further information about the frequency configuration and its effect on the initial read. notes: 1. this delay will only occur when burst length is configured as continuous. see section 4.9.7 for further information about burst length configuration. 2. wait# is configurable. it can be set to assert during or two clk cycles before an output delay. see section for further information about the frequency configuration and its effect on the initial read. figure 18. ac waveform for continuous burst read, showing an output delay with data output configuration set to one clock v ih v il clk (c) note 1 a 19-0 (a) adv# (v) ce# (e) oe# (g) we# (w) v ih v il v ih v il v ih v il v ih v il v ih v il wait# (t) v oh v ol dq 15-0 (d/q) v oh v ol valid output valid output valid output high z valid output valid output r7 r10 r10 note 2 figure 19. ac waveform for continuous burst read, showing an output delay with data output configuration set to two clocks v ih v il clk (c) note 1 a 19-0 (a) adv# (v) ce# (e) oe# (g) we# (w) v ih v il v ih v il v ih v il v ih v il v ih v il wait# (t) v oh v ol dq 15-0 (d/q) v oh v ol valid output high z valid output r7 r10 note 2 r10
28f800f3 ? automotive 38 preliminary 8.6 ac characteristics ? write operations (1, 2) ? automotive temperature notes: 1. see figure 11, ? ac input/output reference waveform for vcc = 3.3 v 0.3 v ? on page 31 for timing measurements and maximum allowable input slew rate. 2. a write operation can be initiated and terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . 5. refer to table 3 for valid a in and d in for block erase or program. 6. write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). hence, t wph = t whwl = t ehel = t whel = t ehwl . 7. t whgl is 15 ns unless resuming a program suspend or erase suspend command; then 30 ns is required before read can be commenced. 8. v pp should be held at v pph1/2 until determination of block erase or program success. # sym parameter valid for all speed and voltage combinations unit notes min max w1 t phwl (t phel ) rst# high recovery to we# (ce#) going low 3 600 ns w2 t elwl (t wlel ) ce# (we#) setup to we# (ce#) going low 4 0 ns w3 t wp (t wlwh ) write pulse width 4 75 ns w4 t vlvh adv# pulse width 10 ns w5 t dvwh (t dveh ) data setup to we# (ce#) going high 5 63 ns w6 t avwh (t aveh ) address setup to we# (ce#) going high 5 75 ns w7 t vleh (t vlwh ) adv# setup to we# (ce#) going high 75 ns w8 t avvh address setup to adv# going high 10 ns w9 t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 ns w10 t whdx (t ehdx ) data hold from we# (ce#) high 0 ns w11 t whax (t ehax ) address hold from we# (ce#) high 0 ns w12 t vhax address hold from adv# going high 3 ns w13 t wph (t whwl ) write pulse width high 6 20 ns w14 t bhwh (t bheh ) wp# setup to we# (ce#) going high 3 200 ns w15 t vpwh (t vpeh )v pp setup to we# (ce#) going high 3 200 ns w16 t whgl (t ehgl ) write recovery before read 7 15 ns w17 t qvbl wp# hold from valid srd 3,8 0 ns w18 t qvvl v pp hold from valid srd 3,8 0 ns
28f800f3 ? automotive preliminary 39 notes: 1. v cc power-up and standby. 2. write block erase or program setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. for read operations, oe# and ce# must be driven active, and we# de-asserted. figure 20. ac waveform for write operations valid address valid address w6 w11 w12 w3 w5 w10 w9 w2 w1 w13 data in data in valid srd w4 w7 w8 w16 a 20-0 (a) v ih v il adv# (v) v ih v il ce# (we#) [e(w)] v ih v il oe# [g] v ih v il we# (ce#) [w(e)] v ih v il data [d/q] v ih v il note 6 note 6 note 1 note 2 note 3 note 4 note 5 rst# [p] v ih v il w15 w18 v pp [v] v pph1/2 v pplk v il wp# [b] v ih v il w14 w17 w19
28f800f3 ? automotive 40 preliminary 8.7 ac characteristics ? reset operation ? automotive temperature notes: 1. these specifications are valid for all product versions (packages and speeds). 2. if t plph is < 100 ns the device may still reset but this is not guaranteed. 3. sampled, but not 100% tested. 4. if rst# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. figure 21. ac waveform for reset operation table 10. reset specifications (1) number symbol parameter notes min max unit p1 t plph rst# low to reset during read (if rst# is tied to v cc , this specification is not applicable) 2,3 100 ns p2 t plrh rst# low to reset during block erase or program 3,4 22 s (a) reset while device is in read mode v ih v il rst # (r) p1 r21 (b) reset during program or block erase, p1 < p2 p2 abort complete v ih v il rst# (r) p1 r21 v ih v il rst # (r) p1 r21 (c) reset during program or block erase, p1 > p2 p2 abort complete
28f800f3 ? automotive preliminary 41 8.8 automotive temperature block erase and program performance (1,2,3) notes: 1. these performance numbers are valid for all speed versions. 2. sampled, but not 100% tested. 3. reference the figure 20, ? ac waveform for write operations ? on page 39 4. typical values measured at t a = +25 c and nominal voltages. subject to change based on device characterization. 5. excludes system-level overhead. 3.3 v v pp 12 v v pp # sym parameter notes typ (4) max typ (4) max unit w19 t whrh , t ehrh1 program time 5 23.5 200 8 185 s block program time (parameter) 5 0.1 0.3 0.03 0.1 sec block program time (main) 5 0.8 2.4 0.24 0.8 sec t whrh , t ehrh2 block erase time (parameter) 5 0.5 1.0 0.5 1.0 sec block erase time (main) 5 1.5 3.0 1.5 3.0 sec t whrh , t ehrh5 program suspend latency 6 10 5 10 s t whrh , t ehrh6 erase suspend time 13 20 10 12 s
28f800f3 ? automotive 42 preliminary 9.0 ordering information valid combinations 56-lead ssop 8 x 8 easy bga automotive 8 m de28f800f3t80 ra28f800f3t80 de28f800f3b80 ra28f800f3b80 de28f800f3t95 ra28f800f3t95 DE28F800F3B95 ra28f800f3b95 r a 2 8 f 8 0 0 f 3 t 8 0 package de = automotive temp., 56-lead ssop ra = automotive temp., 56-ball easy bga product line designator for all intel ? flash products access speed (ns) (80,95) product family f3 = 3 volt fast boot block v cc = 3.0 v - 3.6 v v pp = 3.0 v - 3.6 v or 11.4 v - 12.6 v device density 800 = x16 (8-mbit) t = top blocking b = bottom blocking

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